IBIS Macromodel Task Group

Meeting date: 30 Aug 2011

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                            * Radek Biernacki
Altera:                     * David Banas
Ansys:                        Samuel Mertens
                            * Dan Dvorscak
                            * Curtis Clark
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
Celsionix:                    Kellee Crisafulli
Cisco Systems:                Mike LaBonte
                              Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                        Michael Mirmak
LSI Logic:                    Wenyi Jin
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
			            Vladimir Dmitriev-Zdorov
Micron Technology:            Randy Wolff
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:     * Eckhard Lenski
QLogic Corp.                * James Zhou
Sigrity:                      Brad Brim
                            * Kumar Keshavan
                              Ken Willis
SiSoft:                     * Walter Katz
                            * Todd Westerhoff
                              Doug Burns
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla

The meeting was lead by Arpad Muranyi

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Opens:

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Call for patent disclosure:

- None

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Review of ARs:

AR: Walter - update 123.2.4 and send to Mike LaBonte
  - not done, issues are still topics for discussion today

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New Discussion:

Feedback from IBIS open forum:

Arpad showed BIRD 137.1
- Arpad said Adge of IBM is concerned that we may be "breaking"
  existing models.
- Radek: no need to modify BIRD, we're defining 5.1 behavior not 5.0
- Walter: (agreeing) EDA tools can gracefully handle 5.0 and 5.1
- Bob: each version of the spec should encompass all previous versions
- Walter: need to break with past conventions on backward compatibility
  in this case
- Walter: request Open Forum vote on BIRD as is, we can add section on
  differences
- Bob: can we add a note on 5.0 vs. 5.1 differences (separate BIRD?)
- Walter: motion to table discussion until next meeting and work out
  "differences" section off line.
- Radek: second the motion (approved unanimously)

Arpad showed BIRD 143
- Arpad had added "for version 5.1 and above" language.
- Walter/Radek: unnecessary, handle it the same was as 137.1

Arpad showed BIRD 140
- Arpad expressed his concern that the spec doesn't define where the
  value of the "Corner" parameter is coming from to make the selection
  from the three values following it.
- Walter: EDA tool knows how to map its selection of corner case terms
- Radek: this BIRD won't help by attempting to impose a mapping
- Todd: the problem is that there is no direct mapping between the
  traditional IBIS typ, min, max and AMI typ, slow, fast.
- Arpad: agree on that issue, but I am not talking about mapping.  The
  BIRD is concerned about where the value of Corner comes from.
  Should it be in a GUI where the user makes a selection?  In that
  case why do we need Corner when we have Range, List, and Increment?
  Also, BIRD 124 talks about Corner being a "pre-defined" parameter.
  Where is it pre-defined?
- Walter: that is a BIRD 124 topic, why are we discussing it now?
- (unanimous) table discussion of BIRD 140 until BIRD 124 is discussed

Walter began continued discussion of BIRD 123.2.4
- Walter: Adge from IBM objects to certain Rx parameters
- Kumar: but post processing can't account for CDR changes
- Walter: model maker can build such changes into the clock_times output
  if they wish.


< Curtis had to leave the meeting here...>


- Todd asked questions about where the reference clock and sampled
  clock are located around the CDR box on the drawing.  Todd suggested
  to move the reference clock up from the bottom of the CDR box to the
  arrow that goes into the CDR box.  Walter confirmed that the returned
  clock (from the CDR) is the sampled clock, not the reference clock.

- Fangyi mentioned three comments about this jitter BIRD.
  - After discussions in the last two ATM meetings, it's clear that parameters 
    Rx_DCD, Rx_Rj & Rx_Sj are impairments internal to Rx. Suggest removing 
    the word "external" from their definition in the BIRD. The BIRD also need 
    to explain why they can't be combined with parameters Rx_Clock_Recovery_DCD, 
    Rx_Clock_Recovery_Rj and Rx_Clock_Recovery_Sj. 
  - In time domain simulation, the way Rx_DCD, Rx_Rj & Rx_Sj are handled (by 
    post-processing) is inconsistent with the way Rx_Clock_Recovery_DCD, 
    Rx_Clock_Recovery_Rj and Rx_Clock_Recovery_Sj are handled (by clock_times). 
    It's confusing.
  - Adding Rx Rj in post processing doesn't help to reach BER at 1e-12 by 
    running a few millions bits in time domain simulations because the tail of 
    Tx Rj and ISI can't be captured anyway.
  - Even if IBM internal tool adds Rx Rj in post processing, it is not a good 
    modeling practice to add part of Rx Rj in clock_times and the other part in 
    post processing.

AR: Fangyi to send suggestions on Jitter BIRD to Walter

Meeting ended.

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Next meeting: 6 Sep 2011 12:00pm PT

Next agenda:
1) Task list item discussions

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IBIS Interconnect SPICE Wish List:

1) Simulator directives